There is a continuing need for faster and more precise analog-to-digital converters (ADCs). State of the art ADCs have reached the 10 gigasamples/second (GS/s), 6-12 bit performance. We investigate an implementation of a 100 GS/s 4-6 bit ADC. The use of a cathode ray tube for analog-to-digital conversion was first described in the 1940s. The basic idea is that a bunch of electrons passing through an electric deflection system is directed to a specific detector whence a digital code word emanates. Thus the electron bunch samples the analog deflecting voltage which is then quantized according to the position of the detector receiving the bunch. The most fundamental limit to the number of distinguishable voltage levels is the ratio of the deflecting impulse to the momentum spread due to diffraction of the electron beam. This should allow up to 12 bits at 100 GS/s. At a more practical level the bit resolution and sampling frequency are limited by the brightness of the beam, the uncertainty in the time of emission of each bunch and by the maximum power needed to generate the analog voltage used to deflect the beam. For 50 V deflecting voltage and 100 A timing uncertainty we should be able to achieve 4-5 bits for a 50 GHz bandwidth on the analog voltage (100 GS/s). (C) 2003 American Vacuum Society.