This paper describes the impact of shallow trench isolation depth, different p-well implantation dose and energy, cobalt silicide thickness, and thermal budgets compatible with a 0.18 mum, 0.13 mum, and 90 nm complementary metal-oxide semiconductor (CMOS) technology on the junction leakage current. It is demonstrated that for a 90 nm node a shallow trench depth (e.g., 250 nm) increases the peripheral and corner currents due to a higher surface generation velocity. A higher leakage current and yield loss are obtained for a lower well implantation energy and higher dose. The higher leakage current after silicidation is due to a combination of the shallow junction effect and film roughness. A lower junction leakage current is found for a higher thermal budget because of the better annealing of the p-well implantation-induced defects. This conclusion is derived from a dedicated generation and recombination lifetime and surface generation velocity analysis, which has been developed for shallow junctions in a highly doped p-well and combines current-voltage (I-V) and capacitance-voltage (C-V) characteristics. (C) 2003 The Electrochemical Society.