Silicon loss during gate etch from the active region of a traditional complementary metal-oxide-semiconductor transistor is shown to take place through plasma oxidation of the silicon substrate during the overetch step. The plasma oxidation occurs by an ion-enhanced process with an activation energy of only 0.02 eV This phenomenon is successfully modeled using the traditional Deal-Grove thermal oxidation model, with the inclusion of a depth-dependent reaction rate constant to incorporate the ion-enhancement effect. Plasma oxidation and silicon loss are: reduced by using a shorter polysilicon over-etch time, lower source and bias power, lower substrate temperature, and lower O-2 flow. A viable polysilicon over-etch process was developed that produced vertical gate profiles while reducing the silicon loss by 32%. (C) 2003 American Vacuum Society.