Journal of Vacuum Science & Technology B, Vol.21, No.3, 931-935, 2003
Interface analysis of atomic layer deposited-TiN gate electrodes on ultrathin SiO2 layers
As new gate materials become increasingly interesting in conjunction with tunnel oxides, new deposition techniques have to be developed that deposit thin metal layers without degrading the gate dielectric. Recently, atomic layer deposition has been identified as a suitable, method to deposit refractory metal alloys with well-defined properties. For the first time, a recently developed automated characterization of capacitance-voltage (C-V) curves is employed to identify challenges during the initiation of a metal atomic layer deposition process. While some problems were eliminated by adapting the deposition process, others will require further process or tool modifications to reduce the nonuniformities observed within each wafer. The temperature dependence of the C-V curves indicates an unintended titanium-rich layer at the interface, which disappears after annealing. above 800 degreesC. A further development of the surface pretreatment and subsequent deposition will be necessary to avoid this phenomenon. In this article, a very sensitive procedure to analyze the initiation of a metal atomic layer deposition process is presented. (C) 2003 American Vacuum Society.