Areas of heavy doping, implantation damage, and lattice strains, which are part of any silicon-integrated circuit device, can provide efficient traps for metals and compete for impurities with intentionally introduced gettering sites. In this article we introduce the concept of competitive gettering between gettering sites and devices and perform modeling of competitive gettering in p/p(+) epi wafers, wafers with internal gettering sites, and silicon-on-insulator (SOI) wafers. The impact of the substrate resistivity, density of oxide precipitates, and denuded zone/epi layer width is analyzed for a wide span of cooling ranges. It is found that the major consequence of the effect of gettering by devices is that by the end of cooling, the metal concentration in the device area can substantially exceed its average concentration in the wafer, and device yield could degrade. This can be prevented by optimizing the substrate gettering properties. Although fast cooling rates inherent in rapid thermal processing represent a challenge for gettering, it is shown that optimized gettering can perform well even if the wafer is cooled in a rapid thermal processing system at a rate between 5 and 100 degrees per second. Our modeling results indicate that SOI wafers behave differently than epitaxial or bulk wafers because the buried oxide layer provides a barrier for diffusion of metals between the device area and the substrate. The last section of the article presents an experimental proof of principle of competitive gettering. (C) 2003 The Electrochemical Society.