화학공학소재연구정보센터
Journal of the Electrochemical Society, Vol.148, No.12, G746-G749, 2001
Silicon-on-insulator MOSFET structure for sub-00 nm channel regime and performance perspective
This paper describes performances of the partial-ground-plane (PGP) silicon-on-insulator metal-oxide semiconductor field effect transistor aiming at the demanding radio-frequency applications of the future. In the PGP device, short-channel effects are suppressed by terminating most of the source-and drain-induced electric fields to small heavy doping regions that are localized below the source and drain regions. As a result, the sub-100 nm PGP device with appropriately designed heavy doping regions minimizes the influence of the source and drain parasitic capacitance, even if thin buried oxide layers are used.