The impact of shallow trench isolation (STI) chemical mechanical polishing on gate critical dimension (CD) control for submicron technology was studied. The CD depends on the STI process scheme, whether it is recessed or elevated STI. We investigated the surface topography for both STI schemes at different stages of patterning and how it affected the CD control. Surface topography affected organic bottom antireflective coating (BARC) and resist thickness uniformity, led to variation in the effective exposure dose and caused CD nonuniformity across the wafer [C. A. Mack, Appl. Opt. 25, 1958 (1986)]. We used an atomic force microscope surface scan to study substrate topographical variations. The solution is to optimize BARC and resist thickness by using simulations of topographical swing curves and CD error contour plot. Excellent agreement was found between simulation and experimental results.