Pt/SrTiO3/Pb(Zr-0.52, Ti-0.48)O-3/SrTiO3/Si (MIFIS) ferroelectric gate oxide structures were prepared by an r.f, sputtering method for application of non-destructive read out ferroelectric RAM (NDRO-FRAM) devices. In the MIFIS structure, a SrTiO3 (STO) film was used as a buffer layer to prevent the interaction between the Pb(Zr-0.52, Ti-0.48)O-3 (PZT) film and the Si substrate and also between the PZT film and the Pt top electrode. In the PZT/Si structure, a serious inter-diffusion of Pb into Si substrate was observed by Auger electron spectrometry (AES). However, STO/PZT/STO/Si structures had a perfect perovskite phase and a flat interface of PZT/STO/Si without the inter-diffusion of Pb into the Si substrate. When Pt/STO/PZT/STO/Si structures were post-annealed at 400 degrees C for 30 min after depositing the Pt top electrodes, the leakage current of MIFIS structure was improved to about 10(-8) A/cm(2). The property of the memory window of MIFIS structures was improved due to a low leakage current. When Pt/STO(25 nm)/PZT(160 nm)/STO(25 nm)/Si structures were annealed at 600 degrees C for 1 h and post-annealed at 400 degrees C for 30 min, the maximum value of the memory window was about 2 V at the applied voltage of 7 V. The memory window was increased as increasing the thickness of PZT film since a higher voltage was applied to the thicker PZT film.