Annealing in steam at 800 degreesC up to 8 hours was carried out for pyrogenic oxide layers formed on p and n-type cubic type silicon carbide (3C-SiC) epilayers, which were grown on silicon (100) substrates by low-pressure chemical vapor deposition. After the steam annealing, gold was deposited on the oxide layers (SiO2) to form metal-oxide-semiconductor structures. Simultaneous capacitance-voltage characteristics were measured for these samples to obtain the flat-band voltage (V-fb) and the energy profile of interface trap density (D-it). The effects of the annealing in steam on the electrical characteristics of the SiO2/3C-SiC interface are discussed based on a shift of V-fb and a change in the energy profile of D-it.