As the dimensions of semiconductor devices are reduced, the resistance of conductor lines becomes a critical property in determining the minimum linewidth allowed. Often these conductor lines must traverse substantial topography from prior processing, becoming thinner at the corners or along vertical wails. This creates high resistance or hot spots, which affect the power loss, timing and lifetime of the device. Although considerable emphasis is being placed on planarization techniques such as chemical mechanical polishing, which eliminate hot spots, there are still many processes using little or no planarization. Traditionally wafers are cross-sectioned and viewed by scanning electron microscopy to verify step coverage, or special test structures are patterned and their resistance checked at a later step in the processing. A method of determining relative step coverage changes would be advantageous for process control or identifying the effects of process changes, Data will be presented supporting the use of the mutual inductance test method to measure and map the resistance of conductor films on product wafers immediately after metal deposition. This method allows for rapid detection of process problems, as well as reducing or eliminating the need for separate monitor wafers. Step coverage over the entire wafer can be evaluated quickly and easily during process or equipment characterization, identifying the conditions which give optimum step coverage.