Advanced metallization schemes are needed to take advantage of the miniaturization of microelectronic devices which are performing at increasingly high speeds. The demands on metallization center around (af the increased resistance with lower cross-sectional areas and longer interconnect lengths and (b) stability with the surroundings during processing and use under high current densities and thin him stresses. A threefold attack is being pursued to solve these problems, which also duplicate the issues in packaging of these fast chips with large numbers of inputs and outputs : first is to make use of copper as the interconnection metal; second is to use a multilevel metallization scheme; finally there is a need for a low dielectric constant dielectric. In this paper we present a review of progress made in addressing the first two schemes together with a brief discussion of the third. Copper, a heretofore undesired metal in silicon integrated circuits, seems to show promise, with appropriate processing constraints, of fulfilling the projected needs of ultra-large-scale and giga-scale integration and perhaps even of packaging.