The shrinking of the gate length is not only a challenge for lithography but also for device performance. Subthreshold current increases, so short channel transistors are hard to turn off. In order to reduce the subthreshold current, transistors with buried subchannel implants were modeled and then fabricated by a self-aligned process. This article describes the buried implant metaloxide-semiconductor held effect transistor (MOSFET) model, fabrication, and measured performance. The simple analytic model developed predicts less short channel effects in the buried implant MOSFETs. A novel self-aligned process has, been applied to fabricate the subchannel implants directly under the gate. Identical devices of various gate lengths down to 0.25 mu m were fabricated with and without the buried p(+) implant. The devices with the p(+) implant exhibited a slower threshold voltage roll-off and less subthreshold swing.