A major challenge arising in the interlevel dielectric deposition processes in modern multilevel very large scale integrated technology is the filling of high aspect-ratio spaces without voids between metal lines. Here The main concerns are step coverage and material properties of dielectric films. One approach is the multistep silicon dioxide deposition using plasma enhanced chemical vapor deposition followed by atmospheric pressure CVD from ozone/TEOS. To combine the advantages of different processes and to satisfy the device reliability requirements, one needs to optimize the relative thickness of these sequentially deposited oxide layers. In this work a pro tile simulator, SPEEDIE, is employed to study this multistep process. For the PECVD process a free molecular-flow model based on the combination of a single sticking-coefficient LPCVD model and an ion-induced-deposition model is used. For the atmospheric pressure CVD (APCVD) process a continuum transport model considering both gas-phase diffusion and surface reaction is used with a geometry-variant reaction rate which depends on the ozone (O-3) concentration. The major topography-controlling parameters are calibrated for these sequential processes, and verified through simulation. As an example of application, a prediction of void-forming based on the reliability requirements is generated by the simulator, and can be regarded as a measure of this multistep process. In general an efficient design tool is provided to help optimize the interlevel dielectric deposition processes.