Aggressive scaling of complementary metal-oxide-semiconductor (CMOS) devices requires gate dielectrics with an oxide equivalent thickness, t(ox,eq)similar to 1 nm or less by the product introduction year 2012. Direct tunneling presents a significant performance Limitation in field-effect transistors (FETs) with homogeneous oxide gate dielectrics <1.7 nm. Boron diffusion from p(+) poly-Si gate electrodes in p-channel FETs leads to additional electrical problems for oxide thicknesses <3 nm. interfacial nitridation improves reliability in n-channel FETs; however, by itself, it is not effective in p-type metal-oxide-semiconductor FETs due to boron pileup at the Si-dielectric interface. Proposed solutions include top-oxide surface nitridation and the integration ef composite oxide-nitride dielectrics into CMOS devices. This review discusses the integration of hydrogenated silicon nitride films, prepared by remote plasma-enhanced chemical-vapor deposition, into electrical devices with composite oxide-nitride (ON) gate dielectrics. FET devices with ON dielectrics having the same oxide-equivalent thickness, t(ox-eq) and gate dielectric capacitance as devices with homogeneous oxide gate dielectrics display improved performance and reliability. However, reductions in direct tunneling current due to increased physical thickness are below expectations based on tunneling calculations which assume the tunneling mass of electrons in nitride films: is approximately the same as in SiO2. The combination of a lower electron tunneling mass and a;reduced conduction-band offset energy (i) places important limitations on the extent to which devices with ON gate dielectrics can meet the aggressive scaling needed in advanced CMOS devices, and (ii) raises important questions that have to be addressed when evaluating alternative high-K dielectrics such as Ta2O5, TiO2, and Al2O3. However, tunneling can be reduced by combining monolayer interface nitridation with ON stacks.