In this study the origin of the leakage current of n(+)p diodes and the impact of process conditions on the leakage current is investigated. The influence of isolation modules, namely, conventional local oxidation of silicon (LOCOS) vs. polybuffered LOGOS, and different junction annealing conditions, namely, furnace anneal and rapid thermal anneal, on the diode leakage current is discussed. The diode leakage current level distribution over a wafer is very sensitive to specific processing steps, such as active area definition. For large peripheral diodes in p-type substrate or in p-well, the leakage current strongly depends on junction annealing conditions. The diodes processed with furnace anneal have one order of magnitude lower leakage currents compared to the diodes with rapid thermal anneal. This difference in leakage current is due to different surface generation velocities at the silicon-oxide isolation interface.