In this study, experimental variables pertaining to the formation of nano-pillar arrays using p-type silicon were optimized by controlling current density and chamber temperature. Three factors affecting pillar formation were optimized to improve the efficiency of the pillar array formation process. First, the experiment chamber was designed to maintain a fixed temperature regardless of the external temperature. Second, the Pt counter electrode was changed from a rod type to a mesh type to obtain a uniform distribution of current density. Third, a Cr-Cu alloy electrode was used instead of Cu to increase the electrode current density. The etching area was expanded to form a fine pillar array. This study shows that it is possible to form a nano-pillar array of 600-nm thickness and 44-mu m depth.