This paper investigates the digital circuit-level performance of an inverter realised with n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al0.05Ga0.95Sb tech nology platform in the presence of interface traps and localized strain. The TFET-based inverter is simulated for two different I-OFF values, namely 100 nA/mu m and 10 pA/mu m to target both high-performance and low-power applications. Based on 3D full-quantum simulations, interface traps induce a significant degradation of the voltage gain, noise margin and transient performance despite the better subthreshold slope. The effect of localized strain at the source/channel heterojunction caused by lattice mismatch, while being beneficial in terms of on-current, is unable to recover the circuit-level performance of the ideal case. The device with traps and localized strain is able to outperform the ideal one only in terms of switching transients for I-OFF = 10 pA/mu m.