Role of textured crystalline silicon pyramids size and chemical polishing (CP) for isotropic etching of pyramid peaks/valleys are investigated from carrier-selective contact silicon heterojunction solar cell performance. With an increase of average pyramids size from 2 to 8 mu m, the effective minority carrier lifetimes (tau(eff)) are reduced from similar to 126 to similar to 65 mu s with molybdenum oxide (MoOx) surface passivation layers. After the CP treatment, an increase in the tau(eff) is observed for the same respective textures (from similar to 154 to similar to 99 mu s) due to reduction of charge carrier recombination. The solar cell structure of Ag/ITO/MoOx/n-Si/LiFx/JAl is fabricated at room temperature. With small pyramids (similar to 2 mu m), the cell has shown the better power conversion efficiency of similar to 14.53%, but, after the CP treatment not much efficiency variation is observed. Whereas; the CP treatment is beneficial for medium/large pyramids (similar to 5-8 mu m) based cells, which has enhanced the open-circuit voltage (45-63 mV) after smoothing/rounding of sharp peak/valley surfaces. But, we have observed a reduction in photocurrent due to an increase of light reflection from smoothened pyramid surfaces. Quantum efficiency analysis has provided the better insight with the silicon surface morphology dependent energy conversion. The cells' reverse saturation currents also have analyzed to understand the silicon surface passivation and MoOx/n-Si junction quality. The performance variation of cells is explained by considering low-barrier shunts at the pyramids' peaks/valleys, which influence the junction built-in potential at the depletion region.