Van der Waal (vdW) stacking of two-dimensional (2D) semiconductors owns a natural configuration for construction of vertical (interlayer) tunneling field effect transistors (TFETs). We simulate the vertical TFETs composed by layered black phosphorene (BP) homojunction at sub-10 nm scale from the ab initio quantum transport calculations. For high-performance (HP) application, the on-state currents (I-on) of the vertical BP TFETs outperform those of their planar counterparts under similar gate length (L-g) at sub-5 nm scale. Remarkably, the vertical BP TFETs extend the application field to low-power (LP) devices compared with their planar counterparts. Both I-on (LP) and I-on (HP) of the vertical BP TFETs can fulfill the LP and HP requirements of the international technology roadmap for semiconductors (ITRS) until L-g is scaled down to 5 and 3 nm, respectively.