In this work we present electrical and morphological characterization of thin multilayer structures, SiO2/a-Si:H/SiO2, with possible applications in non-volatile memories devices. All films were obtained by Electron Cyclotron Resonance Chemical Vapor Deposition technique at room temperature. To induce structural changes in the amorphous silicon layer, the gate stacks were subjected to high temperature furnace annealing at 800 degrees C and 1100 degrees C. Three-layer MOS structures were patterned by lithography and subjected to a sintering process in forming gas for 20 min. The structures annealed at high temperature present a memory window in their capacitance-voltage dependencies, which means that these structures could have a possible application as gate insulators in non-volatile memory devices. The morphology of the amorphous layers was studied by atomic force microscopy and scanning electron microscopy which revealed increase of the surface roughness and modifications in the a-Si:H layer after the high temperature process. (C) 2017 Elsevier B.V. All rights reserved.