Replacing expensive silver with inexpensive copper for the metallization of silicon wafer solar cells can lead to substantial reductions in material costs associated with cell production. A promising approach is the use of multi-wire design. This technology uses many wires in the place of busbars, and the copper wires are "soldered" during the low-temperature lamination process to the fingers (printed or plated) or to the transparent conductive oxide (TCO) layer, e.g. in the case of the alpha-Si/c-Si heterojunction cells. We have studied the effects of Si surface morphology (textured or planar) and TCO resistivity (rho) on the contact resistivity (rho(c)) between wires and TCO (In2O3:Sn (ITO), In2O3:F (IFO), and ZnO:Al (AZO)) layers grown on silicon substrates by ultrasonic spray pyrolysis. To determine pc by transmission line model (TLM) measurements, we have developed a specialized TLM test structure which takes into account specifics of laminated contacts. It has been shown that, if the longitudinal resistance of the wires is left out of account, the error in pc determined by TLM measurements may reach tens or hundreds of percent or even more. To eliminate such errors, we have adjusted the TLM measurement procedure. The present results demonstrate the following: (i) In all the groups of our samples, rho(c) increases with rho and the rho(c)(rho) data can be represented by a power-law trend line. (ii) For ITO and IFO, pc is lower in the case of a textured surface: 0.3-6 m Omega cm(2) at rho = 0.2-3 m Omega cm. (iii) In contrast, for the AZO films rho(c) is lower in the case of a planar Si surface: 5-140 m Omega cm(2) at rho = 9-80 m Omega cm. These findings have been used to analyze the series resistance (R-s) of AZO/n-Si heterojunction solar cells. The contribution of rho(c) to R-s has been shown to reach 30-40%. (C) 2016 Elsevier Ltd. All rights reserved.