The presence of variable heat fluxes, such as localized hotspots in integrated circuit (IC) architectures poses a key challenge for thermal management of existing (2D) and emerging three-dimensionally (3D) stacked chips. The use of conventional microchannel or uniform pin fin arrays for microfluidic cooling do not provide adequate surface area for heat transfer in the vicinity of regions of concentrated high power (hotspots), and therefore significant temperature gradients might arise in such zones. In the present investigation, the concept of using a single microfluidic loop for the combined and efficient cooling of hotspot and moderate power (background) areas is proposed, experimentally demonstrated, and supported by a comprehensive numerical model. Two different thermal device vehicles (TDVs) are considered for a range of operating conditions, in which the surface area is locally increased by clustering a dense array of pin fins in the hotspot region for one configuration, while for the other the clustering is uniform in the spanwise direction. De-ionized (DI) water is used as the coolant through a silicon (Si) microgap with 200 tm spacing; the hotspot heat flux is varied from 250 to 750 W/cm(2), while the background heat flux is fixed at 250 W/cm2. Results indicate the capability of the proposed designs to keep the maximum temperature of the combined device below 65 degrees C for an inlet water temperature of 21.3 degrees C, with moderate temperature gradients and pressure drop. In addition, a robust computational fluid dynamics/heat transfer (CFD-HT) model capable of predicting spatially resolved temperature fields arising from heterogeneous heating is validated with relevant experimental data. Detailed benchmark simulations are provided, so they can be reproduced and used for reference in numerical studies with variable pin fin densities. The described methodology represents a cost-effective thermal modeling technique that may be applicable to virtually any type of heat flux distribution or power map, and IC architecture. (C) 2016 Elsevier Ltd. All rights reserved.