화학공학소재연구정보센터
Nature, Vol.536, No.7617, 441-445, 2016
Extending the lifetime of a quantum bit with error correction in superconducting circuits
Quantum error correction (QEC) can overcome the errors experienced by qubits1 and is therefore an essential component of a future quantum computer. To implement QEC, a qubit is redundantly encoded in a higher-dimensional space using quantum states with carefully tailored symmetry properties. Projective measurements of these parity-type observables provide error syndrome information, with which errors can be corrected via simple operations(2). The 'break-even' point of QEC-at which the lifetime of a qubit exceeds the lifetime of the constituents of the system-has so far remained out of reach(3). Although previous works have demonstrated elements of QEC(4-16), they primarily illustrate the signatures or scaling properties of QEC codes rather than test the capacity of the system to preserve a qubit over time. Here we demonstrate a QEC system that reaches the break-even point by suppressing the natural errors due to energy loss for a qubit logically encoded in superpositions of Schrodinger-cat states(17) of a superconducting resonator(18-21). We implement a full QEC protocol by using real-time feedback to encode, monitor naturally occurring errors, decode and correct. As measured by full process tomography, without any post-selection, the corrected qubit lifetime is 320 microseconds, which is longer than the lifetime of any of the parts of the system: 20 times longer than the lifetime of the transmon, about 2.2 times longer than the lifetime of an uncorrected logical encoding and about 1.1 longer than the lifetime of the best physical qubit (the vertical bar 0 >(f) and vertical bar 1 >(f) Fock states of the resonator). Our results illustrate the benefit of using hardware-efficient qubit encodings rather than traditional QEC schemes. Furthermore, they advance the field of experimental error correction from confirming basic concepts to exploring the metrics that drive system performance and the challenges in realizing a fault-tolerant system.