In this article, the authors report for the first time a route to the realization of scalable sub-100 nm Cu-based T-gates using a fully subtractive, "silicon-compatible" process flow. High resolution electron beam lithography and a low-damage RIE etch process are used to transfer a 50 nm line into ICP-CVD silicon nitride. This pattern forms the T-gate foot. A single blanket metallization is then used to form the Schottky contact, the seed layer for the copper electroplating and a barrier to prevent diffusion of the copper once deposited. A constant potential copper electroplating process has been developed for a Ti/Pt seed layer. Copper films have been deposited with bulk sheet resistance rho(sh) similar to 0.1 Omega/square (for a 300 nm film) and resistivity rho = 1.8 x 10(-6) Omega cm. The head dimensions of the T-gate are realized by patterning resist on top of the seed prior to electroplating. Heads of width 500 nm were fabricated and shown to have a total gate resistance of R(g) = 150 Omega mm. (C) 2010 American Vacuum Society. [DOI: 10.1116/1.3501346]