This work proposed and demonstrated a simple yet effective technique that can achieve wafer-scale nanopatterning using electrodeposition and standard microlithographic tools. The proposed technique shrinks the microscale features in the metal layer to the nanoscale and subsequently uses the same metal layer as the etch mask for pattern transfer. As a proof of concept, an array of trenches and holes with initial dimensions of around 700 nm over a 1 X 1 cm(2) wafer area was used to achieve sub-100 nm features in the underlying substrate after the pattern transfer. In addition to the electrodeposition process, only standard i-line lithography, metal deposition and lift-off, and reactive ion etching were used in the experiment. The proposed technique can be extended to the patterning of a general nanoscale pattern except when the pattern density exceeds the resolution limit of the microlithographic tool. In this article, the authors also discuss the line-edge roughness, registration error, and pattern-dependent shrinking rate in the electrodeposition nanopatterning process. The results can be applied to various metallic and semiconducting surfaces and are expected to be advantageous in the fabrication of many nanoscale devices including zero-mode waveguides and nanocantilevers. (C) 2010 American Vacuum Society. [DOI: 10.1116/1.3466883]