In this work the threshold voltage (V-t), the current gain factor (beta), and the drain current (I-D) mismatch trends for 20 nm Gate-Last bulk CMOS technology integrating High-k/metal gate are investigated. The reported results indicate that the high k/metal Gate-Last technology exhibits a reduced metal gate granularity contribution to the V-t mismatch and good performance in terms of the beta mismatch. This study further demonstrates that the I-D variability mainly depends on the mismatch trends of V-t and beta, and on the contributions of the transconductance divided by the drain current (G(m)/I-D) and the source drain series resistance (R-sd) terms. The 20 nm Gate-Last technology exhibits significant improvement in the V-t and beta mismatch performance as compared to the 28 nm Gate-First counterpart. The evolution of the V-t and beta mismatch parameters, iA(Delta vt) and iA(Delta beta I beta), is further analyzed as a function of the electrical oxide thickness EOT (T-ox) along the technology nodes from 90 nm to 20 nm. A clear trend towards a reduction of the y-axis intercept (i.e. offset) of the linear plot of iA(Delta vt) as a function of EOT is observed starting at the 28 nm Gate-First technology, with the offset approaching zero for the 20 nm Gate-Last technology node. This observation point out a considerable decrease of the gate material contribution to mismatch performances. (C) 2015 Published by Elsevier Ltd.