In this work, the effect of copper through-silicon via (TSV) interconnect diameter on stress buildup in Cu TSVs was experimentally determined using a synchrotron-based X-ray microdiffraction technique. A single chip with different Cu TSV diameters (3, 5, and 8 A mu m), all having the same depth and processing conditions was studied. Prior to the measurements, the chip was annealed at 420 A degrees C (30 min), leading to microstructurally stable Cu TSVs. The mean measured hydrostatic stresses were (190 +/- A 25) MPa (3 A mu m diameter), (138 +/- A 19) MPa (5 A mu m diameter), and (209 +/- A 26) MPa (8 A mu m diameter), respectively. No clear relationship between the measured stress and Cu TSV diameter was observed. This trend is attributed to the operation of stress relaxation mechanisms in the polycrystalline Cu TSVs, which includes plastic deformation, grain boundary sliding, void formation/growth, and rate-controlled dislocation motion, which are often neglected in reported finite element analysis studies. Additionally, this study highlights that the thermo-mechanical behavior of Cu TSVs is significantly influenced by their thermal history.