An analytical physics-based flicker noise model has been developed for Double Gate (DG)-FinFETs with multi-layered nitrided high-kappa gate dielectric. The effects of mobility degradation due to velocity saturation, carrier heating, and channel length modulation have been incorporated for an accurate modeling of noise. The mobility fluctuations dependent on the inversion carrier density have been considered. Additionally, the spatial distribution of the trap.density within the dielectric layer has been considered in addition to the energy dependence. This has been validated by the experimental results. Further agreement with recent data for FinFETs is obtained by taking the trap density in the interfacial layer higher than that in the high-kappa layer. This is in contrast to planar transistors where the trap density has a higher value in the high-kappa layer. It has been shown that an optimum choice for the thickness of the dielectric layers is to be made to havc a tolerable noise performance. The flicker noise of DG-FinFETs with nitrided high-kappa dielectric has also been compared to that of DG-FinFETs with SiO2 as the gate dielectric. (C) 2013 Elsevier Ltd. All rights reserved.