A new method for the extraction of flat-band voltage (V-fb) and channel doping concentration (N-d) in Tri-gate Junctionless Transistors (JLTs) is presented. The new method, based on the relationship between the top-effective width (W-top_eff) in accumulation and the effective width (Weir) in partial depletion, enables the extraction of V-fb, and Nd of JLT devices (here as approximate to 0.61 V and approximate to 6.4 x 10(18) cm(-3), respectively). The validity of the new method is also proved by 2D numerical simulations. Furthermore, it is emphasized that the sidewall accumulation current (I-d_side) behavior of Tri-gate JLT devices is found to decrease dramatically near Vfb, allowing an estimation of the V-fb position of JLT devices. (C) 2013 Elsevier Ltd. All rights reserved.