In this study, we developed a method for evaluating the gettering efficiencies between the gettering sites in p well region and the internal gettering sites in the wafer after p-well formation using implantation and evaluated the efficiencies of copper and nickel gettering. The bulk microdefects (BMDs) introduced by heat treatment caused gettering of copper and nickel, which were introduced by intentional spiking of the device with Cu-65 and Ni-60 solutions. For evaluating the gettering efficiencies, we performed trace analyses using Cu-65 and Ni-60 stable isotopes. This study demonstrates the phenomenon of competitive gettering between the p-well region and the internal gettering sites in the wafer. Moreover, the fact that silicon-integrated circuit devices act as efficient metal traps should be taken into account when evaluating the actual gettering ability of silicon wafers. The gettering efficiencies evaluated for the wafers in the no-implantation and boron-implantation groups. The gettering efficiencies of the wafers in the no-implantation and boron-implantation groups are in the range 99.78-100% and 68-100%, respectively. This implies that the gettering efficiency of the wafers is sufficiently high when the competitive gettering between the device and the internal gettering sites is not considered. However, in the competitive-gettering model, 100% gettering is observed only in the p(-)/p(+) epitaxial wafer. The results of the present study indicate that p(-)/p(+) epitaxial wafers have better competitive gettering efficiency than normal polished wafer or rapid thermal annealing (RTA) wafer designed with proximity gettering ability. (C) 2012 Elsevier Ltd. All rights reserved.