In this paper, we present an explicit compact quantum model for the direct tunneling current through dual layer SiO2/high-K dielectrics in Double Gate (DG) structures. Specifically, an explicit closed-form expression is proposed, useful to study the impact of dielectric constants and band offsets in determining the gate leakage, allowing to identify materials to construct these devices, and useful for the fast evaluation of the gate leakage in the context of electrical circuit simulators. A comparison with self-consistent numerical solution of Schrodinger-Poisson (SP) equations has been performed to demonstrate the accuracy of the model. Finally, a benchmarking test of different gate stacks have been proposed searching to fulfill the gate tunneling limits as projected by the International Technology Roadmap for Semiconductors. (C) 2012 Elsevier Ltd. All rights reserved.