Gate-to-channel capacitance C-gc(V-g) data obtained on FD-SOI MOS devices with gate lengths down to 35 nm are first reported. Thus, a 20 numerical simulation procedure allowing to calculate the total device capacitance and parasitic capacitances is developed. This enabled us to discriminate the respective contributions of all parasitic components such as spacer, overlap, inner fringe and buried oxide capacitances in the structure. (C) 2011 Elsevier Ltd. All rights reserved.