Influence of fin width downscaling on hole and electron mobility behavior in FinFETs with (1 0 0), (1 1 0) and (1 1 1) oriented sidewalls is examined. Our effective-mass model reproduces experimental results of UTB SOI pMOSFETs fabricated on (1 0 0) and (1 1 0) surfaces, including the effect of mobility enhancement for certain body thicknesses in (1 1 0) oriented devices. The suitability of well-calibrated EMA for the simulation of hole mobility is confirmed by our results, which opens a possibility of using hole EMA in advanced Monte Carlo simulators. Simulations show that with the downscaling of fin width nFinFETs with (1 0 0) sidewalls and pFinFETs with (1 1 0) and (1 1 1) sidewalls exhibit mobility enhancement in certain fin-width ranges. In contrast, other FinFET configurations experience monotonic mobility degradation with the decreasing fin width. Regarding experimental (1 1 1) FinFETs from our previous work, modeling results suggest that the fin width is highly uniform along the channel, both in nFinFETs and pFinFETs. The impact of electron and hole mobility behavior in UTB FinFETs on SRAM design is also studied. We have found that FinFETs with (1 1 1) active surface enable the most efficient use of the layout area, demanding only four fins for an SRAM cell with matched inverters and high immunity to noise. (C) 2011 Elsevier Ltd. All rights reserved.