This paper demonstrates the thermal-induced mechanical problems resulted from various temperature profiles of reliability test for a system-in-package (SIP) assembly process. The package includes two flip chip mounted chips (underfilled), two memory CSPs, some passive SMDs and 4-layer BT substrate. The flip-chip specimen was taken and the Moire Interferometry was used as methodology to verify the developed Finite Element Model and material property. It also shows that the developed finite element model is capable to simulate the JEDEC standard JESD22-A104 reliability thermal cycle test and then to predict solder fatigue life and to summarize design rules for thermal optimization of package based on the creep model and viscoplastic model of solder while the SIP package design is proceeded. Thermal design for SIP depends on the placement of FC chip (high power) and memory CSP components. Passive SMDs are also included to study the effect of thermal-induced stress. A series of comprehensive parametric studies were conducted in this paper.