The use of high-k dielectrics in 4H-SiC devices has recently attracted interest from the point of view of investigating whether such materials offer enhanced channel conduction when incorporated into 4H-SiC MOSFETS. This study shows that there are benefits and disadvantages of high-k dielectrics beyond just possible enhancement of channel carrier mobility. It is shown that incorporation of high-k dielectrics causes the peak electric field in the forward blocking state to be inside the semiconductor as opposed to the gate oxide of a conventional device. It is also shown that high-k devices are limited by reasons of constraints on cell geometry optimisation to voltages about similar to3kV and that parasitic capacitances within the high-k device are more sensitive to cell layout than in conventional oxide devices.