Present state-of-the-art SiC MOSFETs suffer from low conductance due to poor inversion layer mobility. To improve the conductance, FETs with implanted buried-channel (BC) n-type layers at the SiC/SiO2 interface are being investigated. In this paper, electron conduction in these implanted BC layers is characterized using the Hall effect. When the FET is biased strongly ON, electron conduction occurs simultaneously in both the n-buried-channel and a surface accumulation layer. These two layers have quite different mobilities which complicates the Hall analysis. Here we describe an approach to analyze the Hall data in order to obtain a correct value for the mobility in the surface accumulation layer of the BC device. Results are compared between BC and surface-channel (SC) devices.