In this paper we report on our efforts to reduce trap effects, increase efficiency, and improve the yield and reliability of SiC MESFETs. By minimizing substrate and surface-related trapping effects that have previously been observed in SiC MESFETs, drain efficiencies as high as 68% have been achieved at 3.5 GHz with associated CW power densities of 3.8 W/mm. MESFETs fabricated with this process have passed 1,000 hour High Temperature Reverse Bias test (HTRB) with negligible change in dc or RF parameters. A sampling of these devices have also been running for over 2,000 hours in an RF high temperature operating life test (HTOL) with negligible change in parameters. This MESFET process has been transferred to 3-inch high purity semi-insulating (HPSI) substrates. The quality of this process is demonstrated by the cross-wafer uniformity of the breakdown voltage and a standard deviation in gate threshold voltage of 0.6 V.