Wafer bonding technologies have been recognized to provide new substrates structures suitable for the development of Si power devices. Among the multiple examples that could be listed, the possibility to generate PN junctions without thick epitaxial growth and lateral devices onto dielectrically isolated substrates such as SOI (Silicon On Insulator) are significant examples of the interest proposed by wafer bonding. Thin film substrates obtained with the Smart-Cut(R) technology such as SiCOI (SiC On Insulator) substrates for lateral devices and QUASIC substrates for vertical power devices have already been demonstrated. In. this article, we review the recent developments in the field of SiC power devices using these two kinds of SiC Smart-Cut(R) substrates. Lateral and vertical Schottky diodes have been processed onto SiCOI and QUASIC substrates as a demonstration of feasibility. Simulations, results and prospects are presented in this article.