An optimised enhancement mode JFET structure determined by TCAD simulation is presented. The device has been simulated using Medici TCAD software for fabrication in 4H-SiC. Investigations of critical device parameters have been studied allowing for the proposed optimal structure. The forward current and forward blocking voltage are optimised simultaneously by examining the variation of the device switching power, defined in this context as the product of the forward blocking voltage and the forward current density, as a function of the channel width and trench depth. Channel width is shown to have the most dramatic effect on the device performance for this structure. The optimised structure has a blocking voltage of 650V for zero bias gate voltage with a 250 A cm(-2) forward current, at a gate voltage of 2.5V.