Dielectric stack composed of orthorhombic ZrTiO4 and amorphous Yb2O3 interfacial layer was employed as the gate dielectric for Si n-MOSFET. The gate stack with EOT of 0.79 nm demonstrates a desirable dielectric quality in terms of a low interface trap density (D-it) of 2.4 x 10(11) cm(-2) eV(-1) and a small fixed oxide charge density of 2.8 x 10(11) cm(-2). The promising transistor characteristics are evidenced by the excellent subthreshold swing of 66 mV/dec and good electron mobility of 192 cm(2)/V s at 1 MV/cm. The former is primarily due to the low D-it value while the latter is ascribed to the small amount of fixed oxide charge and the existence of an Yb2O3 interfacial layer; both factors are beneficial to suppress the carrier remote scattering mechanism. From the analysis of positive bias temperature instability with the stress field of 11 MV/cm for 1000 s at 85 degrees C, 12-mV shift in threshold voltage and negligible degradation in subthreshold swing and transconductance prove the satisfactory reliability performance. These prominent electrical characteristics show that the crystalline-based gate stack is eligible for aggressively scaled CMOS devices. (C) 2014 Elsevier B.V. All rights reserved.