Chemically deposited lead sulfide (PbS) thin films were used as the semiconductor active layer in common-gated thin film transistors. The PbS films were deposited at room temperature on SiO2/Si-p wafers. Lift-off was used to define source and drain contacts (gold, Au) on top of the PbS layer with channel lengths ranging from 10 to 80 mu m. The Si-p wafer with a back chromium-gold contact served as the common gate for the transistors. Experimental results show that as-deposited PbS are p-type in character and the devices exhibit typical drain current versus source-drain voltage (I-DS-V-DS) behavior as a function of gate voltage. The values of threshold voltage of the devices were in the range from -7.8 to 1.0 V. depending on the channel length. Channel mobility was approximately 10(-4) cm(2)V(-1) s(-1). The low channel mobility in the devices is attributed to the influence of the microstructure of the nanocrystalline thin films. The electrical performance of the PbS-based devices was improved by thermal annealing the devices in forming gas at 250 degrees C. In particular, channel mobility increased and threshold voltage decreased as a consequence of the thermal annealing. (C) 2010 Elsevier B.V. All rights reserved.