Solid-State Electronics

Solid-State Electronics, Vol.92 Entire volume, number list

ISSN: 0038-1101 (Print)

In this Issue (12 articles)

1 - 4	Electrical characteristics of Al2O3/TiO2/Al2O3 prepared by atomic layer deposition on (NH4)(2)S-treated GaAs Yen CF, Lee MK, Lee JC
5 - 11	Device design assessment of 4H-SiC n-IGBT - A simulation study Usman M, Nawaz M
12 - 19	Application, modeling and limitations of Y-function based methods for massive series resistance in nanoscale SOI MOSFETs Karsenty A, Chelly A
20 - 23	Dependence on an oxide trap's location of random telegraph noise (RTN) in GIDL current of n-MOSFET Gia QN, Yoo SW, Lee H, Shin H
24 - 27	Resistive switching in lateral junctions with nanometer separated electrodes Ziegler M, Harnack O, Kohlstedt H
28 - 34	Analytical model for the threshold voltage of III-V nanowire transistors including quantum effects Marin EG, Ruiz FG, Tienda-Luna IM, Godoy A, Gamiz F
35 - 39	A 2-D semi-analytical model of parasitic capacitances for MOSFETs with high k gate dielectric in short channel Wang M, Ke DM, Xu CX, Wang BT
40 - 46	Low rate deep level transient spectroscopy - a powerful tool for defect characterization in wide bandgap semiconductors Schmidt F, von Wenckstern H, Breitenstein O, Pickenhain R, Grundmann M
47 - 51	ZnO based UV detectors with Surface Plasmon Polariton enhancement on responsivity Li GM, Song JD, Zhang JW, Hou X
52 - 56	High-performance InP/InGaAs co-integrated metamorphic heterostructure bipolar and field-effect transistors with pseudomorphic base-emitter spacer and channel layers Wu YC, Tsai JH, Chiang TK, Chiang CC, Wang FM
57 - 62	Performance optimization for the sub-22 nm fully depleted SOI nanowire transistors Chen CY, Lin JT, Chiang MH
63 - 69	A scaling scenario of asymmetric coding to reduce both data retention and program disturbance of NAND flash memories Doi M, Tanakamaru S, Takeuchi K