| 1 - 7 |
Design of 0.25 mu m 2.7 V 2T2C 4 Mb asynchronous ferroelectric random access memory (FRAM) for mobile applications
Min B, Choi M, Oh S, Chang N, Jeon B, Kim K |
| 9 - 17 |
A 4-Gbps/pin transceiver with a multi-level simultaneous bi-directional scheme for serial link applications
Kim WS, Kim JH, Kim CH, Kim S |
| 19 - 24 |
A sensing circuit for MRAM based on 2MTJ-2T structure
Jang EJ, Lee SY, Kim HJ, Shin H, Lee S, Kim D |
| 25 - 29 |
A 1.8 V 128; Mb mobile DRAM with hidden-precharged triple pumping scheme and dual-path hybrid current sense amplifier
Chun KC, Sim JY, Yoon H, Lee HS, Hong SP, Lee KC, Yoo JH, Seo DI |
| 31 - 36 |
Design of three-dimensional real-time disparity system using stereo images
Kang B, Woo K, Hong C, Hong D, Yang H |
| 37 - 42 |
Design of multi-standard NTSC/PAL video encoder
Kang B, Kim J, Yang H |
| 43 - 47 |
Design of a 3GPP turbo decoder using SW-BCJR algorithm with small memory block
Kim HJ, Lee C |
| 49 - 53 |
Dual edge-triggered flip-flop with modified NAND keeper for high-performance VLSI
Kim JI, Kong BS |
| 55 - 59 |
Design of fourth-order Delta Sigma modulator for the D/A conversion of audio signals
Lee JA, Sohn YC, Kim SH, Kim D, Min KS, Kim DM |
| 61 - 67 |
A high performance CPW 4x sub-harmonic mixer using anti-parallel diode pair (APDP) for the V-band
Sul WS, Lee HS, Kim SC, Han HJ, Uhm WY, An D, Kim SD, Shin DH, Park HM, Rhee JK |
| 69 - 73 |
Q-band high conversion gain active sub-harmonic mixer
Lee BH, Kim SC, Lee MK, Sul WS, Lim BO, Uhm WY, Rhee JK |
| 75 - 81 |
2x oversampling 2.5 Gbps clock and data recovery with phase picking method
Moon YH, Kang JK |
| 83 - 86 |
A new synthesis technique of sequential circuits for low power and testing
Cho S, Park S |
| 87 - 90 |
Design methodology adopting normalized power-delay-and-area product (N-PDAP) for digital-circuit optimization
Kim SH, Lee JA, Kim D |
