검색결과 : 6건
| No. | Article |
|---|---|
| 1 |
Steep subthreshold slope characteristics of body tied to gate NMOSFET in partially depleted SOI Song L, Hu ZY, Liu ZL, Xin HW, Zhang ZX, Zou SC Solid-State Electronics, 130, 15, 2017 |
| 2 |
PSP-SOI: An advanced surface potential based compact model of partially depleted SOI MOSFETs for circuit simulations Wu W, Li X, Gildenblat G, Workman GO, Veeraraghavan S, McAndrew CC, van Langevelde R, Smit GDJ, Scholten AJ, Klaassen DBM, Watts J Solid-State Electronics, 53(1), 18, 2009 |
| 3 |
An area efficient body contact for low and high voltage SOI MOSFET devices Daghighi A, Osman M, Imam MA Solid-State Electronics, 52(2), 196, 2008 |
| 4 |
Temperature impact on the Lorentzian noise induced by electron valence-band tunneling in partially depleted SOI p-MOSFETs Guo W, Cretu B, Routoure JM, Carin R, Simoen E, Claeys C Solid-State Electronics, 51(9), 1180, 2007 |
| 5 |
Electron valence-band tunnelling excess noise in twin-gate silicon-on-insulator MOSFETs Simoen E, Claeys C, Lukyanchikova N, Garbar N, Smolanka A, Der Agopian PG, Martino JA Solid-State Electronics, 50(1), 52, 2006 |
| 6 |
Analytical model for C-V characteristic of fully depleted SOI-MOS capacitors Afzal B, Zahabi A, Amirabadi A, Koolivand Y, Afzali-Kusha A, El Nokali M Solid-State Electronics, 49(8), 1262, 2005 |