| 1 |
Analysis of the dynamic avalanche of carrier stored trench bipolar transistor (CSTBT) during clamped inductive turn-off transient
Xue P, Fu GC
Solid-State Electronics, 129, 35, 2017 |
| 2 |
FinFETs using reverse substrate layer with improved gate capacitance characteristics for subthreshold application
Wei X, Zhong J, Luo J, Wu H, Zhu HL, Zhao C, Yin HZ
Solid-State Electronics, 104, 116, 2015 |
| 3 |
Performance optimization for the sub-22 nm fully depleted SOI nanowire transistors
Chen CY, Lin JT, Chiang MH
Solid-State Electronics, 92, 57, 2014 |
| 4 |
Simulation based performance comparison of transistors designed using standard photolithographic and coarse printing design specifications
Wondmagegn WT, Satyala NT, Stiegler HJ, Quevedo-Lopez MA, Forsythe EW, Pieper RJ, Gnade BE
Thin Solid Films, 519(6), 1943, 2011 |
| 5 |
Capacitance measurements in nanometric silicon devices using Coulomb blockade
Hofheinz M, Jehl X, Sanquer M, Cueto O, Molas G, Vinet M, Deleonibus S
Solid-State Electronics, 51(4), 560, 2007 |
| 6 |
Extraction of the gate capacitance coupling coefficient in floating gate non-volatile memories: Statistical study of the effect of mismatching between floating gate memory and reference transistor in dummy cell extraction methods
Rafhay Q, Beug MF, Duane R
Solid-State Electronics, 51(4), 585, 2007 |
| 7 |
Temperature and polarization dependent polynomial based non-linear analytical model for gate capacitance of A1(m)Ga(1-m)/GaN MODFET
Chattopadhyay MK, Tokekar S
Solid-State Electronics, 50(2), 220, 2006 |
| 8 |
Modeling for reduced gate capacitance of nanoscale MOSFETs
Dai YH, Chen JN, Ke DM, Xu C, Sun JE
Solid-State Electronics, 50(7-8), 1472, 2006 |
| 9 |
Accurate modeling of gate capacitance in deep submicron MOSFETs with high-K gate-dielectrics
Hakim MMA, Haque A
Solid-State Electronics, 48(7), 1095, 2004 |
