검색결과 : 2건
| No. | Article |
|---|---|
| 1 |
Managing annealing pattern effects in 45 nm low power CMOS technology Morin P, Cacho F, Beneyton R, Dumont B, Colin A, Bono H, Villaret A, Josse E, Bianchini R Solid-State Electronics, 54(9), 897, 2010 |
| 2 |
Modelling of the 1T-Bulk capacitor-less DRAM cell with improved performances: The way to scaling Ranica R, Villaret A, Malinge P, Candelier P, Masson P, Bouchakour R, Mazoyer P, Skotnicki T Solid-State Electronics, 49(11), 1759, 2005 |