검색결과 : 5건
| No. | Article |
|---|---|
| 1 |
A novel model of the high-voltage VDMOS for the circuit simulation Liu SY, Zhu RX, Jia K, Huang D, Sun WF, Zhang CW Solid-State Electronics, 93, 21, 2014 |
| 2 |
Trench superjunction VDMOS with charge imbalance cells Sun WF, Zhu J, Qian QS, Cao PF, Liu SY, Su Z, Lu SL, Shi LX Solid-State Electronics, 64(1), 14, 2011 |
| 3 |
Theoretical analysis of the vertical LOCOS DMOS transistor with process-induced stress enhancement Reggiani S, Denison M, Gnani E, Gnudi A, Baccarani G, Pendharkar S, Wise R Solid-State Electronics, 54(9), 950, 2010 |
| 4 |
Evaluation of the ruggedness of power DMOS transistor from electro-thermal simulation of UIS behaviour Donoval D, Vrbicky A, Marek J, Chvala A, Beno P Solid-State Electronics, 52(6), 892, 2008 |
| 5 |
Scalable general high voltage MOSFET model including quasi-saturation and self-heating effects Chauhan YS, Anghel C, Krummenacher F, Maier C, Gillon R, Bakeroot B, Desoete B, Frere S, Desormeaux AB, Sharma A, Declercq M, Ionescu AM Solid-State Electronics, 50(11-12), 1801, 2006 |