| 1 |
Compact modeling of the subthreshold characteristics of junctionless double-gate FETs including the source/drain extension regions
Bae MS, Yun I
Solid-State Electronics, 156, 48, 2019 |
| 2 |
Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs
Qin CL, Wang GL, Hong PZ, Liu JB, Yin HX, Yin HZ, Ma XL, Cui HS, Lu YH, Meng LK, Xiang JJ, Zhong HC, Zhu HL, Xu QX, Li JF, Yan J, Zhao C, Radamson HH
Solid-State Electronics, 123, 38, 2016 |
| 3 |
A new T-Shaped Source/Drain Extension (T-SSDE) Gate Underlap GAA MOSFET with enhanced subthreshold analog/RF performance for low power applications
Kumar M, Haldar S, Gupta M, Gupta RS
Solid-State Electronics, 101, 13, 2014 |
| 4 |
Temperature effect of metal-oxide-semiconductor field-effect-transistors' gate current evaluated with the mask dimensions
Yeh CC, Neih CF, Chen YY, Gong J
Solid-State Electronics, 52(2), 215, 2008 |
| 5 |
Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations
Kranti A, Armstrong GA
Solid-State Electronics, 50(3), 437, 2006 |
| 6 |
Polyreoxidation process step for suppressing edge direct tunneling through ultrathin gate oxides in NMOSFETs
Maitra K, Bhat N
Solid-State Electronics, 47(1), 15, 2003 |
| 7 |
A dynamic source-drain extension MOSFET using a separately biased conductive spacer
Gonzalez F, Mathew SJ, Chediak JA
Solid-State Electronics, 46(10), 1525, 2002 |
