| 1 |
A thorough study of Si nanowire FETs with 3D Multi-Subband Ensemble Monte Carlo simulations
Donetti L, Sampedro C, Ruiz FG, Godoy A, Gamiz F
Solid-State Electronics, 159, 19, 2019 |
| 2 |
Detailed characterisation of Si Gate-All-Around Nanowire MOSFETs at cryogenic temperatures
Boudier D, Cretu B, Simoen E, Veloso A, Collaert N
Solid-State Electronics, 143, 27, 2018 |
| 3 |
Multi-Subband Ensemble Monte Carlo simulations of scaled GAA MOSFETs
Donetti L, Sampedro C, Ruiz FG, Godoy A, Gamiz F
Solid-State Electronics, 143, 49, 2018 |
| 4 |
Analysis and optimization of RC delay in vertical nanoplate FET
Woo C, Ko K, Kim J, Kim M, Kang M, Shin H
Solid-State Electronics, 136, 81, 2017 |
| 5 |
Geometry and temperature effects on the threshold voltage characteristics of silicon nanowire MOS transistors
Wong H, Yu QQ, Dong SR, Kakushima K, Iwai H
Solid-State Electronics, 138, 35, 2017 |
| 6 |
The impact of stress-induced defects on MOS electrostatics and short-channel effects
Esqueda IS
Solid-State Electronics, 103, 167, 2015 |
| 7 |
Compact model of short-channel effects for FDSOI devices including the influence of back-bias and fringing fields for Si and III-V technology
Hiblot G, Lacord J, Akbal M, Rafhay Q, Boeuf F, Ghibaudo G
Solid-State Electronics, 107, 1, 2015 |
| 8 |
Quantum simulation study of single halo dual-material gate CNTFETs
Wang W, Li N, Xia CP, Xiao GR, Ren YZ, Li H, Zheng LF, Li J, Jiang JJ, Chen XP, Wang K
Solid-State Electronics, 91, 147, 2014 |
| 9 |
In depth static and low-frequency noise characterization of n-channel FinFETs on SOI substrates at cryogenic temperature
Achour H, Cretu B, Routoure JM, Carin R, Talmat R, Benfdila A, Simoen E, Claeys C
Solid-State Electronics, 98, 12, 2014 |
| 10 |
A new T-Shaped Source/Drain Extension (T-SSDE) Gate Underlap GAA MOSFET with enhanced subthreshold analog/RF performance for low power applications
Kumar M, Haldar S, Gupta M, Gupta RS
Solid-State Electronics, 101, 13, 2014 |
