화학공학소재연구정보센터
검색결과 : 10건
No. Article
1 High temperature solar thermoelectric generator - Indoor characterization method and modeling
Pereira A, Caroff T, Lorin G, Baffle T, Romanjek K, Vesin S, Kusiaku K, Duchemin H, Salvador V, Miloud-Ali N, Aixala L, Simon J
Energy, 84, 485, 2015
2 In-depth physical investigation of GeOI pMOSFET by TCAD calibrated simulation
Grandchamp B, Jaud MA, Scheiblin P, Romanjek K, Hutin L, Le Royer C, Vinet M
Solid-State Electronics, 57(1), 67, 2011
3 Mobility in ultrathin SOI MOSFET and pseudo-MOSFET: Impact of the potential at both interfaces
Hamaide G, Allibert F, Andrieu F, Romanjek K, Cristoloveanu S
Solid-State Electronics, 57(1), 83, 2011
4 High mobility CMOS: First demonstration of planar GeOI p-FETs with SOI n-FETs
Le Royer C, Damlencourt JF, Vincent B, Romanjek K, Le Cunff Y, Grampeix H, Mazzocchi V, Carron V, Nemouchi F, Hartmann JM, Arvet C, Vizioz C, Tabone C, Hutin L, Batude P, Vinet M
Solid-State Electronics, 59(1), 2, 2011
5 High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate
Romanjek K, Hutin L, Le Royer C, Pouydebasque A, Jaud MA, Tabone C, Augendre E, Sanchez L, Hartmann JM, Grampeix H, Mazzocchi V, Soliveres S, Truche R, Clavelier L, Scheiblin P, Garros X, Reimbold G, Vinet M, Boulanger F, Deleonibus S
Solid-State Electronics, 53(7), 723, 2009
6 Investigation of 1/f noise in germanium-on-insulator 0.12 mu m PMOS transistors from weak to strong inversion
Gyani J, Valenza M, Soliveres S, Martinez F, Le Royer C, Augendre E, Romanjek K, Drazek C
Solid-State Electronics, 53(12), 1268, 2009
7 105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers
Le Royer C, Clavelier L, Tabone C, Romanjek K, Deguet C, Sanchez L, Hartmann JM, Roure MC, Grampeix H, Soliveres S, Le Carval G, Truche R, Pouydebasque A, Vinet M, Deleonibus S
Solid-State Electronics, 52(9), 1285, 2008
8 Low frequency noise characterization and modelling in ultrathin oxide MOSFETs
Contaret T, Romanjek K, Boutchacha T, Ghibaudo G, Boeuf F
Solid-State Electronics, 50(1), 63, 2006
9 Characterization of the effective mobility by split C(V) technique in sub 0.1 mu m Si and SiGePMOSFETs
Romanjek K, Andrieu F, Ernst T, Ghibaudo G
Solid-State Electronics, 49(5), 721, 2005
10 New approach for the gate current source-drain partition modeling in advanced MOSFETs
Romanjek K, Lime F, Ghibaudo G, Leroux C
Solid-State Electronics, 47(10), 1657, 2003